Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
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software_version_and_target_device
betaFALSE build_version2086221
date_generatedFri May 4 14:22:01 2018 os_platformWIN64
product_versionVivado v2017.4 (64-bit) project_id8e91174d2f784bd1898cf91be5ee452e
project_iteration26 random_id29b6963fd03c5e90a2b13c6c34a8b8bd
registration_id29b6963fd03c5e90a2b13c6c34a8b8bd route_designTRUE
target_devicexc7z020 target_familyzynq
target_packageclg400 target_speed-1
tool_flowVivado

user_environment
cpu_nameIntel(R) Xeon(R) CPU E5-2630 v2 @ 2.60GHz cpu_speed2594 MHz
os_nameMicrosoft Windows 8 or later , 64-bit os_releasemajor release (build 9200)
system_ram34.000 GB total_processors1

vivado_usage
gui_handlers
abstractcombinedpanel_remove_selected_elements=1 abstractfileview_reload=4 addrepositoryinfodialog_ok=2 addsrcwizard_specify_hdl_netlist_block_design=1
addsrcwizard_specify_or_create_constraint_files=1 addsrcwizard_specify_simulation_specific_hdl_files=1 applyrsbmultiautomationdialog_checkbox_tree=1 basedialog_apply=5
basedialog_cancel=14 basedialog_ok=78 basedialog_yes=27 basereporttab_rerun=4
cmdmsgdialog_ok=22 cmdmsgdialog_open_messages_view=2 constraintschooserpanel_add_files=1 coretreetablepanel_core_tree_table=9
creatersbportdialog_create_vector=4 creatersbportdialog_direction=6 creatersbportdialog_from=16 creatersbportdialog_port_name=11
creatersbportdialog_type=1 designtimingsumsectionpanel_worst_negative_slack=1 expruntreepanel_exp_run_tree_table=16 filesetpanel_file_set_panel_tree=174
flownavigatortreepanel_flow_navigator_tree=89 gettingstartedview_open_project=4 hcodeeditor_search_text_combo_box=2 ipstatussectionpanel_upgrade_selected=5
logmonitor_monitor=2 mainmenumgr_edit=6 mainmenumgr_file=8 mainmenumgr_help=2
mainmenumgr_open_recent_project=1 mainmenumgr_report=6 mainmenumgr_tools=16 mainmenumgr_window=4
mainwinmenumgr_layout=2 msgtreepanel_discard_user_created_messages=1 msgtreepanel_message_severity=1 msgtreepanel_message_view_tree=18
msgview_warning_messages=1 navigabletimingreporttab_timing_report_navigation_tree=9 pacommandnames_add_module_to_bd=1 pacommandnames_add_sources=6
pacommandnames_auto_connect_target=11 pacommandnames_auto_update_hier=29 pacommandnames_create_top_hdl=3 pacommandnames_customize_core=1
pacommandnames_customize_rsb_bloc=1 pacommandnames_goto_source=5 pacommandnames_log_window=1 pacommandnames_open_hardware_manager=2
pacommandnames_open_project=1 pacommandnames_regenerate_layout=9 pacommandnames_save_rsb_design=1 pacommandnames_set_as_top=1
pacommandnames_show_product_guide_src=1 pacommandnames_zoom_fit=5 paviews_project_summary=1 planaheadtab_refresh_changed_modules=33
programdebugtab_open_target=7 programdebugtab_program_device=24 programfpgadialog_program=29 projectsummarydrcpanel_open_drc_report=1
projectsummarytimingpanel_open_timing_summary_report=2 projectsummarytimingpanel_project_summary_timing_panel_tabbed=3 projectsummaryutilizationpanel_project_summary_utilization_panel_tabbed=1 rdicommands_copy=1
rdicommands_custom_commands=5 rdicommands_delete=2 rdicommands_save_file=1 rdicommands_settings=6
rdicommands_undo=7 rsbaddmoduledialog_module_list=3 rsbapplyautomationbar_run_connection_automation=1 rungadget_show_error_and_critical_warning_messages=1
rungadget_show_warning_and_error_messages_in_messages=1 saveprojectutils_save=2 selectmenu_highlight=13 settingsdialog_project_tree=2
settingsprojectiprepositorypage_add_repository=2 settingsprojectiprepositorypage_refresh_all=3 simpleoutputproductdialog_close_dialog_unsaved_changes_will=3 simpleoutputproductdialog_generate_output_products_immediately=3
srcchooserpanel_add_hdl_and_netlist_files_to_your_project=2 srcchooserpanel_add_or_create_source_file=1 srcchooserpanel_create_file=1 srcchooserpanel_make_local_copy_of_these_files_into=1
srcchooserpanel_scan_and_add_rtl_include_files_into=3 srcmenu_ip_documentation=5 srcmenu_ip_hierarchy=30 stalerundialog_no=1
syntheticagettingstartedview_recent_projects=1 syntheticastatemonitor_cancel=2 systembuildermenu_add_ip=4 systembuildermenu_add_module=3
systembuildermenu_create_port=12 systembuildermenu_ip_documentation=2 systembuilderview_add_ip=4 systembuilderview_orientation=5
systemtab_report_ip_status=1 systemtab_upgrade_later=1 systemtreeview_system_tree=4 taskbanner_close=4
tclobjecttreetable_treetable=4 timingitemflattablepanel_table=11 xpg_ipsymbol_show_disabled_ports=2 xpg_tabbedpane_tabbed_pane=2
java_command_handlers
addmoduletoblockdesign=1 addsources=6 autoconnecttarget=11 coreview=1
createblockdesign=2 createtophdl=3 customizecore=1 customizersbblock=11
editcopy=1 editdelete=11 editpaste=3 editundo=7
launchprogramfpga=29 openblockdesign=15 openexistingreport=3 openhardwaremanager=22
openproject=5 openrecenttarget=6 programdevice=9 recustomizecore=8
regeneratersblayout=9 reportipstatus=1 runbitgen=34 savefileproxyhandler=3
saversbdesign=8 settopnode=1 showproductguide=1 showsource=5
showview=5 toolssettings=6 upgradeip=5 viewtaskimplementation=1
zoomfit=5
other_data
guimode=8
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=2 export_simulation_ies=2
export_simulation_modelsim=2 export_simulation_questa=2 export_simulation_riviera=2 export_simulation_vcs=2
export_simulation_xsim=2 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=Mixed srcsetcount=4 synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog target_simulator=XSim totalimplruns=9 totalsynthesisruns=9

unisim_transformation
post_unisim_transformation
bufg=6 carry4=16 dsp48e1=1 fdre=145
fdse=70 gnd=18 ibuf=7 lut1=68
lut2=50 lut3=51 lut4=80 lut5=61
lut6=101 mmcme2_adv=1 muxf7=2 obuf=1
obufds=4 ramb18e1=3 vcc=16
pre_unisim_transformation
bufg=6 carry4=16 dsp48e1=1 fdre=145
fdse=70 gnd=18 ibuf=7 lut1=68
lut2=50 lut3=51 lut4=80 lut5=61
lut6=101 mmcme2_adv=1 muxf7=2 obuf=1
obufds=4 ramb18e1=3 vcc=16

power_opt_design
command_line_options_spo
-cell_types=default::all -clocks=default::[not_specified] -exclude_cells=default::[not_specified] -include_cells=default::[not_specified]
usage
bram_ports_augmented=0 bram_ports_newly_gated=0 bram_ports_total=6 flow_state=default
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=215 srls_augmented=0
srls_newly_gated=0 srls_total=0

ip_statistics
HDMI_test/1
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=HDMI_test x_ipproduct=Vivado 2017.4 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
IP_Integrator/1
bdsource=USER core_container=NA da_board_cnt=2 iptotal=1
maxhierdepth=0 numblks=8 numhdlrefblks=5 numhierblks=0
numhlsblks=2 numnonxlnxblks=0 numpkgbdblks=0 numreposblks=8
numsysgenblks=0 synth_mode=OOC_per_IP x_iplanguage=VERILOG x_iplibrary=BlockDiagram
x_ipname=design_1 x_ipvendor=xilinx.com x_ipversion=1.00.a
Interface/1
core_container=NA iptotal=1 x_ipcorerevision=1805031620 x_iplanguage=VERILOG
x_iplibrary=hls x_ipname=Interface x_ipproduct=Vivado 2017.4 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
TicTacToe/1
core_container=NA iptotal=1 x_ipcorerevision=1805031636 x_iplanguage=VERILOG
x_iplibrary=hls x_ipname=TicTacToe x_ipproduct=Vivado 2017.4 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
clean_button/1
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=clean_button x_ipproduct=Vivado 2017.4 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
clean_button/2
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=clean_button x_ipproduct=Vivado 2017.4 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
clean_button/3
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=clean_button x_ipproduct=Vivado 2017.4 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
clean_button/4
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=clean_button x_ipproduct=Vivado 2017.4 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
clk_wiz_v5_4_3_0/1
clkin1_period=8.000 clkin2_period=10.000 clock_mgr_type=NA component_name=design_1_clk_wiz_0_0
core_container=NA enable_axi=0 feedback_source=FDBK_AUTO feedback_type=SINGLE
iptotal=1 manual_override=false num_out_clk=4 primitive=MMCM
use_dyn_phase_shift=false use_dyn_reconfig=false use_inclk_stopped=false use_inclk_switchover=false
use_locked=true use_max_i_jitter=false use_min_o_jitter=false use_phase_alignment=true
use_power_down=false use_reset=true
hls_ip_2017_4/1
core_container=NA hls_input_arch=others hls_input_clock=10.000000 hls_input_fixed=1
hls_input_float=0 hls_input_part=xc7z020clg400-1 hls_input_type=cxx hls_syn_clock=9.634000
hls_syn_dsp=1 hls_syn_ff=48 hls_syn_lat=3 hls_syn_lut=1227
hls_syn_mem=3 hls_syn_tpt=none iptotal=1
hls_ip_2017_4/2
core_container=NA hls_input_arch=others hls_input_clock=10.000000 hls_input_fixed=1
hls_input_float=0 hls_input_part=xc7z020clg400-1 hls_input_type=cxx hls_syn_clock=6.782000
hls_syn_dsp=0 hls_syn_ff=34 hls_syn_lat=5 hls_syn_lut=1233
hls_syn_mem=0 hls_syn_tpt=none iptotal=1

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-ruledecks=default::[not_specified] -upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
dpop-1=1 dpop-2=1 zps7-1=1

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=5 bufgctrl_util_percentage=15.63
bufhce_available=72 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=16 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=8 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=16 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=4 mmcme2_adv_fixed=0 mmcme2_adv_used=1 mmcme2_adv_util_percentage=25.00
plle2_adv_available=4 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsp48e1_only_used=1 dsps_available=220 dsps_fixed=0 dsps_used=1
dsps_util_percentage=0.45
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=1
memory
block_ram_tile_available=140 block_ram_tile_fixed=0 block_ram_tile_used=1.5 block_ram_tile_util_percentage=1.07
ramb18_available=280 ramb18_fixed=0 ramb18_used=3 ramb18_util_percentage=1.07
ramb18e1_only_used=3 ramb36_fifo_available=140 ramb36_fifo_fixed=0 ramb36_fifo_used=0
ramb36_fifo_util_percentage=0.00
primitives
bufg_functional_category=Clock bufg_used=5 carry4_functional_category=CarryLogic carry4_used=16
dsp48e1_functional_category=Block Arithmetic dsp48e1_used=1 fdre_functional_category=Flop & Latch fdre_used=145
fdse_functional_category=Flop & Latch fdse_used=70 ibuf_functional_category=IO ibuf_used=7
lut1_functional_category=LUT lut1_used=68 lut2_functional_category=LUT lut2_used=48
lut3_functional_category=LUT lut3_used=51 lut4_functional_category=LUT lut4_used=80
lut5_functional_category=LUT lut5_used=61 lut6_functional_category=LUT lut6_used=101
mmcme2_adv_functional_category=Clock mmcme2_adv_used=1 muxf7_functional_category=MuxFx muxf7_used=2
obuf_functional_category=IO obuf_used=1 obufds_functional_category=IO obufds_used=4
ramb18e1_functional_category=Block Memory ramb18e1_used=3
slice_logic
f7_muxes_available=26600 f7_muxes_fixed=0 f7_muxes_used=2 f7_muxes_util_percentage=<0.01
f8_muxes_available=13300 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_logic_available=53200 lut_as_logic_fixed=0 lut_as_logic_used=330 lut_as_logic_util_percentage=0.62
lut_as_memory_available=17400 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=106400 register_as_flip_flop_fixed=0 register_as_flip_flop_used=215 register_as_flip_flop_util_percentage=0.20
register_as_latch_available=106400 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=53200 slice_luts_fixed=0 slice_luts_used=330 slice_luts_util_percentage=0.62
slice_registers_available=106400 slice_registers_fixed=0 slice_registers_used=215 slice_registers_util_percentage=0.20
fully_used_lut_ff_pairs_fixed=0.20 fully_used_lut_ff_pairs_used=37 lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0
lut_as_logic_available=53200 lut_as_logic_fixed=0 lut_as_logic_used=330 lut_as_logic_util_percentage=0.62
lut_as_memory_available=17400 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
lut_as_shift_register_fixed=0 lut_as_shift_register_used=0 lut_ff_pairs_with_one_unused_flip_flop_fixed=0 lut_ff_pairs_with_one_unused_flip_flop_used=122
lut_ff_pairs_with_one_unused_lut_output_fixed=122 lut_ff_pairs_with_one_unused_lut_output_used=122 lut_flip_flop_pairs_available=53200 lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_used=164 lut_flip_flop_pairs_util_percentage=0.31 slice_available=13300 slice_fixed=0
slice_used=102 slice_util_percentage=0.77 slicel_fixed=0 slicel_used=69
slicem_fixed=0 slicem_used=33 unique_control_sets_used=16 using_o5_and_o6_fixed=16
using_o5_and_o6_used=79 using_o5_output_only_fixed=79 using_o5_output_only_used=0 using_o6_output_only_fixed=0
using_o6_output_only_used=251
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

router
usage
actual_expansions=1511296 bogomips=0 bram18=3 bram36=0
bufg=0 bufr=0 congestion_level=0 ctrls=16
dsp=1 effort=2 estimated_expansions=324156 ff=215
global_clocks=5 high_fanout_nets=0 iob=16 lut=372
movable_instances=698 nets=787 pins=4234 pll=0
router_runtime=0.000000 router_timing_driven=1 threads=2 timing_constraints_exist=1

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7z020clg400-1
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=design_1_wrapper -verilog_define=default::[not_specified]
usage
elapsed=00:01:30s hls_ip=0 memory_gain=518.621MB memory_peak=764.117MB